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 Expert  723897

Expert in Semiconductor IC Process and Operations Engineering, Bipolar & CMOS, Si & SiGe, RF, MEMS, Solar


Available for your Consulting and Expert Witness Needs

California (CA)
CA
USA
Education Work History Career AccomplishmentsPublicationsConsulting Services Expert Witness

Summary of Expertise:

Listed with other top experts in: 

Developed short courses and trained product engineers on basic yield improvement methods using SPC(Statistical Process Control). Developed a seminar and trained design engineers for design for manufacturability. Trained engineers at foundries on use of basics of SPC and implementing them. Trained engineers at foundries on details of specific fab process steps developments or improvements during technology transfer.

Visited various foundries world wide and brought up, co-developed or transferred mixed-signal and analog process Bipolar, CMOS and BiCMOS technologies. Also negotiated wafer prices, secured wafer supply capacity, and held periodic technical review meetings. Lined up and selected strategic fab/technology partners for future products requirements. Formed strategic partnerships for total manufacturing and joint sale on selected products.

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doping agent

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drive diffusion

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integrated-circuit manufacturing

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manufacturing

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microelectronic device manufacturing

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operational auditing

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operations management

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predeposition diffusion

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production process

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semiconductor diffusion

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semiconductor dopant lateral diffusion

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semiconductor doping

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semiconductor material manufacturing

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semiconductor wafer processing


Show Secondary and Basic Areas of Expertise
Localities:
Expert may consult nationally and internationally, and is also local to the following cities: San Jose, California;  San Francisco, California;  Sacramento, California;  Oakland, California;  Stockton, California;  Fremont, California;  Modesto, California;  Salinas, California;  Santa Rosa, California;  and Hayward, California.

Education:
Year   Degree   Subject   Institution  
1971   BS   Physics   St. Xavier's College, Gujarat Univ  
1973   MS   Physics   Gujarat University  
1977   MS   Electrical Engineering   Univ. of Cincinnati, OH  

Work History:
Years   Employer   Department   Title   Responsibilities

2005 to

 

(Undisclosed)

 


 

Consulting, V P of Operations

 

One of the two key executives. Helped start the company. Company is designing very advanced RF IC's using Si, Si-Ge and GaAs based processes. Establish new foundry relationships with targeted foundries with Si and SiGe technologies meeting RF IC product needs. Help prepare V C presentations and participate in the meetings. Visit potential customers, vendors, fab/technology suppliers to form strategic partner relationships. Help prepare Sales presentations and other sales material.

1989 to 2005

 

MicroLinear Corp

 

Operations Engg

 

Sr. Director

 


1986 to 1989

 

Philips/Signetics

 

Technology Development/Fab 16

 

Section Manager - Diff and TF, YE and PCM.

 

Managed two engg groups for advanced products and technology development Fab: Bipolar, CMOS, BiCMOS. Diffusion, Oxidation, Anneal & Thin Films process engineering groups. Also, managed Electrical Test and Yield Enhancement engineering group.

1980 to 1986

 

Advanced Micro Devices ((A M D)

 

Technology Development/Fab-6

 

Section Manager

 

Fab 6 Process Engg Section Head: CMOS. BiCMOS for advanced DRAM's, SRAM's and micro-processors chips. Set-up and started half of the fab, managed all white-room ( diffusion, oxidations, anneals, very thin gate oxides, Implants, Thin-films ( ACVD, PCVD, PELPCVD, LPCVD) process engineering groups. Introduced megasonic cleans, low stress PELPCVD processes, very thin gate oxides.

Technology Development Group: Bipolar & BiCMOS for PROM and PAL products. Co-authored one patent on Pt-Si fuse formation using novel processing technique.

1978 to 1980

 

National Semi

 

Advanced Bipolar Memory

 

Sr. Process engr

 


1977 to 1978

 

Univ. of Cincinnati

 

ECE Dept

 

Research Associate

 

Set-up Epitaxial reactor.

1977 to 1977

 

Rensselaer Polytechnic Institute

 

ECE Dept

 

Research Associate

 


1974 to 1976

 

Univ of Cincinnati

 

ECE Dept

 

Research Assistant

 



Career Accomplishments:
Associations/Societies

Member of FSA's Tech Sub-Cmt. IEEE Member.


Publications:
Publications and Patents Summary

One patent on Pt-Si formation. One paper & thesis published on TCE Gettered MOS gate oxide and its impact on improving gate leakage current.


Consulting Services:
Recent Client Requests:
  • Expert for consulting on Die attach of Bipolar Transistor using AuSn versus AuSi.
Click the green button above to contact Expert for a free initial screening call regarding your expert consulting needs.  Expert is available for consulting to corporate, legal and government clients.  Remember, your initial screening call to speak with Expert is free.

Expert Witness:
Click the green button above to contact Expert for a free initial screening call regarding expert testimony, litigation consulting and support, forensic services, or any related expert witness services.  A few litigation needs include product liability, personal injury, economic loss, intellectual property (patent, trademark, trade secret, copyright), and insurance matters.  Remember, your initial screening call to speak with Expert is free.

International Experience:
Years   Country / Region   Summary
1989 to 2005   Japan, Korea, Singapore, Taiwan, Malaysia   Visited wafer foundries and other suppliers: 1. To bring-up, co-develop or transfer mixed-signal and analog process Bipolar, CMOS and BiCMOS technologies. 2. To negotiate wafer prices, secure wafer supply capacity, and hold periodic technical review meetings. 3. To line-up and select strategic fab/technology partners for future products requirements. 4. To form strategic partnerships for total manufacturing and joint sale on selected products.
to   Germany, Austria   Visited wafer foundries: 1. To bring-up, co-develop or transfer mixed-signal and analog process Bipolar, CMOS and BiCMOS technologies. 2. To negotiate wafer prices, secure wafer supply capacity, and hold periodic technical review meetings. 3. To line-up and select strategic fab/technology partners for future products requirements.
2005 to   India   Visit to train RF design engineers in selected aspects of manufacturing to shape/improve their view on designing for better yield/cost.

Language Skills:
Foreign Language   Description
Hindi  
Gujarati   1st language.

Additional Skills and Services:
Training/Seminars

For internal company use only at previous companies: Developed short courses and trained product engineers on basic yield improvement methods using SPC(Statistical Process Control). Developed a seminar and trained design engineers for design for manufacturability. Trained engineers at foundries on use of basics of SPC and implementing them. Trained engineers at foundries on details of specific fab process steps developments or improvements during technology transfer.

Supplier and Vendor Location and Selection

In Mixed Signal Analog and RF areas, strategized foundry, assembly and test vendor selection and established long term relationships.


 

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